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  • VERILOG TUTORIAL 1DaNang University of Technology Prepaired by: Kien T.Nguyen, Lab AssistantThanh Vu, Lab AssistantAnh H.D.Nguyen, Lab AssistantAP-ECE

  • MaterialsTools:Specification: Word, AbiWord, Open Office RTL coding: HDL TurboWriter, Notepad++, Vim, Emacs, conTEXTSimulation: iVerilog, ModelSim, Quartus Simulator, ISE SimulatorSynthesis: Quartus, Xilinx ISEWebsite:www.asic-world.comwww.dut.udn.vn/ece

  • ReferencesEE271 A Brief Logic Tutorial, Brian J.ToccoStephen Brown, Fundamentals of Digital Logic with Verilog, Verilog reference, App A.Introductory Digital Systems Laboratory, MITDon Thomas, The Verilog Hardware Description Language, Carnegie Mellon University.IEEE Verilog 1364 - 1995IEEE Verilog 1364 - 2001EVITA-Verilog interactive tutorial (software)Verilog Tutorial, www.asic-world.com

  • Lectures OutlineIntroduction to logic circuitVerilog Tutorial.Lab 1: Design and simulate mux module.Lab 2: Gate level vs behavior levelLab 3: Introduction DE1 Kit

  • 1.Introduction to logic circuitA binary switchA Light controlled by a switchLight = XWhat is logic circuit ?

  • 1.Introduction to logic circuit (contd)Light (Z) = X.YLight (Z) = X + YBasic Logic gate, symbol & function

  • 1.Introduction to logic circuit (contd)Z = X.YZ = X+YZ = X+Y = X.Y + X.YZ = X+Y = X.Y + X.Y

  • 1.Introduction to logic circuit (contd)Ex1: Check again !!Ex2: Think more!! And can you draw circuits?Truth Table in Digital circuit

    Truth table is a mathematics table which is used to specify the functionality of a digital logic circuit.

    X YX YX.YX.YX+YX+YX+YX+Y0 00 101 111 00 10 0

    xyzx.y.zx+y+zx.y + z(x+y).z000011110011001101010101

  • 1.Introduction to logic circuit (contd)Decimal system: S={0;1;2;3;.;9};123 = 1x10^2 + 2x10^1 + 2x10^0Binary system: S = {0;1};1001 = 1x2^3 + 0x2^2 + 0x2^1 + 1x2^0 = 8 + 1 = 9Convert Decimal to Binary:11 : 2 remain1= 5 : 2 remain 1 => 1011= 2: 2 remain 0= 1:2 remain 1=0Practice covert 1101 to decimal, 15 to binary ?

  • 2.Verilog Tutorial2.1 Structural Models2.2 Behavioral Models2.3 Variable2.4 Operator2.5 Complex Statement2.6 Testbench

  • 2.1 Structural ModelsOverview: also call Gate level Models

  • 2.1 Structural Models (contd)

  • 2.1 Structural Models (contd)

  • 2.2 Behavioral Models

  • 2.2 Behavioral Models (contd)

  • 2.2 Behavioral Models (contd)

  • 2.2 Behavioral Models (contd)

  • 2.2 Behavioral Models (contd)Sensitivity list

  • 2.3 Variablereg: store value until another value is assigned to it. Ex: reg sda;wire: connect signal togethertime: 64 bit wide register use to store time value. Only use in simulateinteger: 32 bit registerreal: for store real numeric valuerealtime: time value using real typeArrays: Ex reg sda [7:0]; wire sda_wire [7:0];Vector: Ex reg [7:0] sda;

  • 2.4 OperatorArithmetic Operators: Addition + Subtraction Multiplication * Division :Modulo %Relative Operators: Lower < Larger >Lower or equal =Read more in EVITA-Verilog: Chapter 5, Section 3

  • 2.4 Operator (contd)Equality operatorsEqual: ==Not equal: !=Logical operatorsAnd: && .Ex: A = 2; B = 0; A&&B = 0Or: ||.Ex: A = 2; B = 0; A||B = 1Not: !Bitwise operatorsAnd: &Ex: A = 2b10; B = 2b00; A&B = 2b00Or: |Ex: A = 2b10; B = 2b00; A|B = 2b10Not: ~Ex: A = 2b10; B = ~A = 2b01Xor: ^Ex: A = 2b10; B = 2b00; A|B = 2b10Xnor: ~^Ex: A = 2b10; B = 2b00; A|B = 2b01Read more in EVITA-Verilog: Chapter 5, Section 3

  • 2.4 Operator (contd)Redunction operatorsAnd: & Ex: A = 4b1010; B = &A = A[3] & A[2] & A[1] & A[0] = 1b0 Or: | Ex: A = 4b1010; B = |A = 1b1 Nand: ~& Ex: A = 4b1010; B = ~&A = 1b1 Nor: ~| Ex: A = 4b1010; B = ~|A = 1b0 Xor: ^ Ex: A = 4b1010; B = ^A = 1b0 Xnor: ~^ Ex: A = 4b1010; B = ~^A = 1b1 Shift operatorsShift left: >Concatenation and Replication OperatorsRead more in EVITA-Verilog: Chapter 5, Section 3

  • 2.5 Complex statementsAlways and initial blocks (already know)The if-else statement (already know)The case statementLoop statements

  • The case statementmodule mux4_to_1 (out, i0, i1, i2, i3, s1, s0); output out; input i0, i1, i2, i3; input s1, s0; reg out; always @(s1 or s0 or i0 or i1 or i2 or i3) begin case ({s1, s0}) 2'b00: out = i0; 2'b01: out = i1; 2'b10: out = i2; 2'b11: out = i3; default: out = 1'bx; endcase end endmodule

  • Loop statementsWhy loop

    integer count;initial begin count = 0; while (count < 128)begin $display("Count = %d", count); count = count + 1; end endFor loop

    integer count;initial begin count = 0; for (count = 0;count < 128; count = count +1 )begin $display("Count = %d", count); count = count + 1; end end

  • 2.6 Test benchUUT is an instance module which map to the real modules for simulating

  • Test bench Mux modeldutfbcselstimulusmeasuremux_tb

  • Icarus SimulationCompile verilog file to data out file

    Generate vcd file for simulation

    Run gtkwave simulation with that vcd fileSee more in: How to run Icarus?

  • Lab 1Coding mux module and mux_tb module using notepad++.Complile verilog file with iverilogiverilog [path]/mux.vGenerate vcd file with vvpvpp a.outSimulation mux module in GTKWAVEgtkwave dump.vcdSave the result waveform to a picture

  • Lab 2Coding gate level mux module using notepad++. (Slide 10)Compile, Simulation mux module in GTKWAVESave result waveform to a picture. Compare the results between Lab 1 and Lab 2. What are differences? Why ? Why do we have to assign the delay value ?

    -Specification: describes the function of your circuit. Example:RTL coding: use HDL to describe the circuit follow the specificationSimulation: to verify about you code typing, structure of code, algorithmSynthesis: compile you circuit and program it to a chip*Overview about digital logic circuit.Basic knowledge about Verilog, one of many HDL which popular in the worldLab 1: make friendly with coding Verilog in an verilog editor, and simulate it in an open software Icarus.Lab 2: Write again Lab 1 but in gatelevel to compare with Lab 1s result *- This is a simple logic circuit that can represent by an expression. If we assign light logic 0 when it turn off and logic 1 when it turn on, we will have the expression Light = x*If we connect 2 switches in serial, the light will turn on or logic 1 when both of switches are close or in logic 1. Otherwise, the light is turn off or in logic 0. So we have the concept AND logic. Introduce about the symbol and truth table.Symbol is use when you want to draw a digital circuit.Truth table tell us the function of this circuit.If we connect 2 switches in parallel, *- From AND, OR, people give more logic gate : NAND, NOR, XOR, XNOR, NOT (or Inverter)*Apply basic gate to check again the function of XOR and XNORHow about other function ? Complete the truth table. Can you write the circuits?*- Now, you only need to know Verilog is use to generate digital circuit. With Verilog we can write the schematic, we dont need to draw circuit which its very sotifical and hard to debug in the very large circuit. With Verilog we will code the circuit and debug it in a very short time. - Verilog is one of many Hardware Description Language such as: VHDL, System Verilog, System C, ABEL, PLI, .. - When the IC is very high integrated in nm, drawing all the circuit is horrible, but coding is nice. *Left side for input signal: a,b,selRight side for output signal: fThe function of this circuit is f = a if sel = 0, f = b if sel =1. sel mean selection.Primitive logics are smallest circuit, the cell logic, They are often supported in library of compile and simulate tool. AND, OR, NOT, NAND, NOR, XOR, XNORDelay value after # use to simulate the delay when signal run from input to output.The order of signal in instances is follow exactly the order of the initial module*