sase2011-dsp con fpga

7/25/2019 Sase2011-Dsp Con Fpga

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Introduction to

DSP Using FPGAs

Guillermo GichalUTN FRBB


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Program

Morning

Introduction to DSP What is DSP? How is it done?

h! use FPGAs "or DSP# Comments on DSP algorithms and FPGA implementations.

Issues related to DSP using FPGAs Clock freqenc!" sampling" #it cont" arithmetic operations.

FPGA Design "lo$ "or DSP a%%licationsDesign alternati$es% HD&s" dedicated tools" etc.

Basic design e&am%les


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Program

A"ternoon

Intro to 'ilin& S!stem Generator 'ilin( S!sgen and its interaction with )atla#" Simlink * +S,.

Use o" 'ilin& S!sGen "or DSP -se of S!sgen for simlation and s!nthesis.

(&am%les

Additional To%ics ther tools and additional comments


4/74

Re"erences

)*n the Roots o" Digital Signal Processing+ Parts , - ./+ I((( 0ircuits and S!stems Maga1ine+

2ol3 4 Num5er , and 6

Ber7ele! Design Technolog!+ Inc3 $hite%a%ers+ $$$35dti3com

DSP8FPGA3com articles+ $$$3ds%8"%ga3com

Andra7a 0onsulting articles+ $$$3andra7a3com

Programma5le 9ogic Design 9ine articles+ $$$3%ldesignline3com

FPGA and Structured ASI0 :ournal articles+ $$$3"%ga;ournal3com

A0M erters/+ Te&as Instruments

)The Scientist and (ngineer?s Guide to DSP/+ Ste>en Smith+ $$$3DSPGuide3com

I((( %a%ers+ $$$3ieee&%lore3ieee3org

)Digital Signal Processing $ith FPGAs/+ U$e Ma!er8Baese+ S%ringer

'ilin&+ Altera and 9attice documentation+ $$$3&ilin&3com+ $$$3altera3com+ $$$3latticesemi3com

The Math$or7s documentation+ $$$3math$or7s3com

etc3
http://www.mathworks.com/http://www.latticesemi.com/http://www.altera.com/http://www.xilinx.com/http://www.dspguide.com/http://www.acmqueue.com/http://www.fpgajournal.com/http://www.pldesignline.com/http://www.andraka.com/http://www.dsp-fpga.com/http://www.bdti.com/


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9et?s go o>er some 5ac7ground

in"ormation on DSP

A Pro%os o" the )Treatise

on 0u5ic Form@ 5! :uan de

errera

Sal>ador Dali+ ,C


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hat is DSP#

From $i7i%edia

Digital signal processing /DSP0 is the std! of signals in a digital

representation and the processing methods of these signals. DSP

and analog signal processing are s#fields of signal processing.

DSP incldes s#fields like% adio and speech signal processing"

sonar and radar signal processing" sensor arra! processing"

spectral estimation" statistical signal processing" digital image

processing" signal processing for commnications" #iomedicalsignal processing" seismic data processing" etc.


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hat is DSP#

Digital Signal Processing Enot Processors

DIGITA9 Digital domain" as opposed toanalog. ,$er!thing is digital nowada!s1

SIGNA9A ph!sical qantit! that changes

o$er time.

PR*0(SSING Do something with the

signal" maniplate it in sefl wa!s.


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hat is DSP#

e ha>e al$a!s )%rocessed/ signalsH

Hto commnicate

Hto nderstand and smmari2e scientific data

Hfor entertainment

333etc.

No$ $e do it digitall!+ research ne$ methods and algorithms and

constantl! "ind ne$ challenging and com%le& a%%lications3

Man! o" the mathematical methods and algorithms used "or signal

%rocessing are $ell 7no$n+ and $ere de>elo%ed $ithin other conte&ts3

3efer to the Circits and S!stems maga2ine seriesOn the Roots of DSP" #!

Andreas Antonio for a histor! of DSP.


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hat is DSP#

SoH

We want to maniplate signals1 which are sall! real signals like

adio" temperatre" crrents and $oltages" seismic" sonar" 3Fwa$es /commnications0" images" #iological" etc.

We take them into the digital domain #ecase it makes life easier

for s.

We maniplate /process0 the signals sing algorithms and methods

to transform them in wa!s that are sefl for or prposes.


10/74

hat is DSP#

3eal signals Analog signal conditioning

Bandwidth, amplitude, etc.

Make this as simple as possible

Digital domain Sampling /discreti2ation and qanti2ation0

We try to do this as early as possible in the process

Processing Signal processing algorithms and methods

Implies mathematical operations, delay lines. Lots of theory and tools implementation issues!

An interestin blend of theory and practice

And $e $ant to do all this this in the sim%lest+ chea%est mannerH


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hat is DSP#

DSP is made %ossi5le 5! mathematical research+ the

digital com%uter and I0 technolog!

Discreti2ation and interpolation has #een part of mathematics since classicaltimes

Work #! Forier" Poisson" &arent and others dring the 4566 an 4766s

Work dring 4866s #! 9!qist" Shannon" :ode and others.

Calclating machines" ,9+AC and the modern digital compter

+ntegrated circit technolog! in 48;6s

9merical filtering methods dring 48o# easier


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o$ is

DSP Done#

DSP algorithmsH

Filters

FIR IIR

Discrete Fourier Trans"orm


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DSP algorithmsH

Direct Digital

S!nthesis EDDS

Digital U%8con>erter

o$ is

DSP Done#


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DSP algorithmsH

*FDM Recei>er Eused in 5enchmar7 article

o$ is

DSP Done#


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DSP a%%lications

EDSPs Bac7 to the Future+ A0M


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DSP algorithmsH sha%e DSP architectures Fast multi%lication and other DSP tas7s

inle cycle, multiply accumulate "MA#$, AL%s, shifter, wide accumulators

Fle&i5le and e""icient memor! access&ata delay lines, 'I'(s, dedicated address eneration "in)erted, circular addressin$, hih bandwidth "multiplebusses, coefficient $

(""icient 9oo%ing

*ero o)erhead loopin, addressin and calculations in parallel

Real time+ s%eedHigh clock freqenc!" parallelism "MA#, AL%, address eneration, IM&$, special instruction sets "low end &+$,

multiple eecution units "hih end, -LIW

Streamlined I* and inter"acesMust connect to A, &A#s and transfer data in and out in real time and with little o)erhead

Data "ormats&i)erse precisions, accumulator uard bits. upport for roundin, saturation and shiftin.

peed, cost power/0 'ied point, 1umeric fidelity/0 floatin point

o$ is

DSP Done#


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hat else does $i7i%edia sa!H

DSP algorithms ha$e traditionall! rn on speciali2ed processors

called digital signal processors /DSPs0. Algorithms reqiring more

performance than DSPs cold pro$ide were t!picall! implementedsing applicationspecific integrated circit /AS+Cs0. =oda! howe$er

there are a nm#er of technologies sed for digital signal

processing.

=hese inclde more powerfl general prpose microprocessors"

fieldprogramma#le gate arra!s /FPGAs0" digital signal controllers

/mostl! for indstrial apps sch as motor control0" and stream

processors" among others.

o$ is

DSP Done#


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No$ada!s there are se>eral o%tions "or DSP a%%lications

ASI0s EA%%lication S%eci"ic Integrated 0ircuits

ASSP EA%%lication S%eci"ic Standard Product

DSP EDigital Signal Processor

FPGA EField Programma5le Gate Arra!

GPP and M0Us $ith DSP enhancements

igh end 0PUs

e ha>e to choose the right %lat"orm "or each %ro5lemJ

S%eed# 0ost# Po$er# Tools# Time to mar7et# Fle&i5ilit!# *ther tas7s#

o$ is

DSP Done#


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o$ do $e choose#

What are m! needs?

What are each options@ strengths?

What are each options@ limitations?

What are mystrengths and weaknesses?

Are there tools a$aila#le?

What will #e arond the DSP portion of m! design?

Strengths and limitations o" each o%tion change

o>er timeH and the! change =uic7l!J

U%date !our in"ormation and don?t ta7e an!thing "or granted

o$ is

DSP Done#


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FPGA Technolog! *>er>ie$

Reading

Sal>ador Dali+ ,K,


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FPGA *>er>ie$

An FPGA is a )sea o" gates/3 9ots o" logic thatcan 5e connected together to "orm di""erentcom5inational and se=uential digital circuits3

An FPGA inside

Function generation Ecom5inational logic

Registers and latches Ese=uential logic

Memor! 0loc7 management

Po$er management

DSP "unctionsJJJ


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FPGA *>er>ie$

'ilin& S%artan L FPGA General FPGA Architecture


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FPGA *>er>ie$

'ilin& S%artan L Memor!


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FPGA *>er>ie$

'ilin& S%artan L 0loc7 Management


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FPGA *>er>ie$

'ilin& S%artan L Routing


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FPGA DSP

Functions

igh end FPGAs Function generators - registers

'ilin& 2irte&

Altera Strati& III


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DSP 9o$ cost FPGAs

'ilin& S%artan L has multi%liers

Altera 0!clone III

FPGA DSP

Functions


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DSP 9o$ cost FPGAs

9attice(0P8DSP

FPGA DSP

Functions


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DSP 9o$ cost FPGAs

9attice(0P8DSP >s S%artan L E9attice Article

FPGA DSP

Functions


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DSP 9o$ cost FPGAs

'ilin& S%artan LA8DSP E'tremeDSP DSP6K slices

FPGA DSP

Functions

G S


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DSP igh end FPGAs

'ilin& and Altera 5oth ha>e igh (nd FPGAs$ith DSP enhancements

igh s%eed multi%liers

Fle&i5le Multi%l!Accumulate logic

DSP 5loc7 cascading and interconnection

Rounding and saturation units

Barrel shi"ter

Su%%ort "or "loating %oint multi%lication

Ad>anced cloc7 and %o$er management

Su%%ort "or additional DSP Intellectual Pro%ert! EIP

FPGA DSP

Functions

FPGA DSP


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DSP igh end FPGAs

Altera Strati& III DSP Bloc7s

FPGA DSP

Functions

FPGA DSP


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DSP igh end FPGAs

'ilin& 2irte& DSP6K Slice

FPGA DSP

Functions


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Do $e $ant to use an FPGA#

To$er o" (nigmas

Sal>ador Dali+ ,K,


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FPGA *>er>ie$

Remem5erH a DSP is essentiall! a se=uential%rocessing machine+ $ith su%%ort to e&ecuteEalthough most DSP do se>eral things in %arallel

Analog De>ices?AD.,&& architecture


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FPGA *>er>ie$

H 5ut some are >er! %o$er"ul %rocessingmachinesJ

TI?s 0C4,. AD?s Blac7"in


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hen to use

FPGAs

hen do $e choose FPGAs to do DSP#

FPGAs are good "orH

9ots o" %arallel %rocessing Man! sim%le and rigid+ re%etiti>e tas7s

igh sam%ling rates and data 5and$idth

Fi&ed %oint o%erations

Im%lementing small DSPs 5loc7s $ithin lots o" digital logic

Protot!%ing or re%lacing ASI0s Fle&i5le or d!namic hard$are con"iguration

Ma%%ing a 5loc7 diagram directl! into hard$are

Multirate s!stems

0on"igura5le $ord lengths and %recision

hat else#


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hen do $e choose FPGAs to do DSP#

FPGAs are not that good "orH

Se=uential tas7s Ei" $e ha>e 0 code a>aila5le

0om%le& tas7s $ith lots o" decision ma7ing and 5ranching

2er! lo$ %o$er a%%lications E5ut that is changing

Floating %oint o%erations

H

hat else#

hen to use

FPGAs


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hen to use

FPGAs

From 'ilin& slides33


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FPGA >s DSP

From an A0Mendor?s article EAltera

HighHighEasyHighLowShortRISC/GPP

HighLowEasyLowLowestShortMCU

HighHighHardHighHighShortFPGA

HighLowEasyLowHighShortDSP

LowLowEasiestLowHighShortestASSP

LowLowHardestLowHighLongestASIC

FlexibilityPowerEase o UsePri!ePeror"an!e#i"e to Mar$et

hen to use

FPGAs


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FPGA >s DSP

From FPGA >endor EAltera at FPGA8DSP3com article

hen to use

FPGAs


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FPGA >s DSP

From FPGA >endor E'ilin& at DSP (ngineering article

FPGAs "or high end a%%lications

Im%ro>ed %er"ormance E%arallelism

9o$er s!stem %o$er Ecom%ared to DSP clusters

Recon"igura5le hard$are Ee>ol>ing standards

0ustom 5it %recision

*%timi1ation o" com%utation hard$are Enot %ossi5le in DSPsEdistri5uted arithmetic+ etc+ see Andra7a

igh I* 5and$idth

hen to use

FPGAs


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FPGA >s DSP and other o%tions

ASI0s EA%%lication S%eci"ic Integrated 0ircuits

ASSP EA%%lication S%eci"ic Standard Product

DSP EDigital Signal Processor

FPGA EField Programma5le Gate Arra!

GPP and M0Us $ith DSP enhancements EdsPI0+ ARM DSP e&tensions

igh end 0PUs EIntel+ AMD doing %rocessing "or audio and images

0omments#

*%inions#

*ther issues#

hen to use

FPGAs


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e?>e decided to use an FPGAJhat issues a""ect our im%lementation#

Portrait o" Mrs3 Mar! Sigall

Sal>ador Dali+ ,6K


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Im%lementation

Issues

Issues that a""ect the im%lementation on an FPGA

Data "re=uenc!+ sam%ling "re=uenc!+ cloc7 "re=uenc!

Num5er re%resentation+ $ord $idths+ %recision+ rounding

Arithmetic o%erations+ %arallel+ serial+ distri5uted+ o>er"lo$+under"lo$+ saturation

9oo78U% ta5les+ 5loc7 ram or distri5uted memor!+ o%timi1ations

I l i


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Im%lementation

Issues

Fre=uencies

Sam%ling "re=uenc!Fre=uenc! at $hich sam%les o" the data areta7en and %rocessed3

0loc7 "re=uenc!Fre=uenc! o" the s!stem cloc7 E0loc7 dri>ing theFPGA registers0

Data rate 3ate at which new data arri$es and needs to #eprocessed

Multi%le "re=uenciesse$eral different data rates" mltiplesampling freqencies andor different clock domains

These rates and "re=uencies $ill a""ect and limitthe %ossi5le architectures and solutions

I l t ti


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Im%lementation

Issues

Sam%ling "re=uenc!

Data sam%ling must meet the N!=uist criterion

(&ternal data must 5e 5and limited 5e"ore it is sam%led E"ilters

Data can 5e o>ersam%led or undersam%led

*>ersam%ling used to increase SNR or reduce e""ects o"=uanti1ation noise

Undersam%ling used in IF or RF signals

Multirate s!stems ha>e se>eral sam%ling "re=uencies Relationshi% 5et$een them a""ects data trans"ers 5et$een them

FPGA $ill dri>e AD0 control signals

AD0 timing+ relationshi% 5et$een s!stem cloc7 and AD0 signals

Meet data setu% and hold times in FPGA

I l t ti


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Im%lementation

Issues

Sam%ling "re=uenc!

Manage s!nchroni1ation to s!stem cloc7

Integer di>ision o" s!stem cloc7 ESam%le rate 0loc7 6 is eas!J

Manage multi%le sam%le rates EDo$nsam%ling 5! 6L is hard

Use as!nchronous FIF*s to get data to and "rom %rocessinglogic to the DA0 and AD0

FPGA $ill %ro5a5l! dri>e AD0 and DA0 control signals

AD0 and DA0 timing

Relationshi% 5et$een s!stem cloc7 and con>erter signals

Must meet data setu% and hold times "or FPGA and DA0

I l t ti


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Im%lementation

Issues

0loc7 "re=uenc!

igher cloc7 "re=uencies $ill ena5le higher sam%ling rates

igher cloc7 "re=uencies $ill consume more %o$er

Use as "e$ cloc7 domains as %ossi5le and control rates $ith)0loc7 (na5le/ in%ut

0loc7 di>iders generate )0(/ signals at lo$er rates

9ogic can 5e reused

I l t ti


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Im%lementation

Issues

0loc7 "re=uenc!

I" sam%ling "re=uenc! is lo$er than s!stem cloc7+ se>eralcloc7s can 5e used to %rocess the data

I l t ti


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Im%lementation

Issues

Data rate

Use"ul data might come at lo$er "re=uencies than thesam%ling "re=uenc!

Some data ma! not need to 5e sam%led at same as others

I l t ti


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Im%lementation

Issues

0loc7 "re=uenc! and sam%le rate

Data at cloc7 rate

Filter result a>aila5lee>er! on cloc7 c!cle

Data at 0( rate

Filter result ta7es se>eral cloc7 c!cles to com%lete

Note Data has N 5its and each FF re%resents N registers

I l t ti


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Im%lementation

Issues


0loc7 at high s%eed

Data at 0( rate Esam%le "re=uenc!

(ach coe""icientis multi%lied at

0(. rate

Multi%lication isim%lemented $ithshi"t8add logic+ and

ta7es se>eral c!cles to com%lete

Filter result ta7es se>eral cloc7 c!cles

to com%lete

I l t ti


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Im%lementation

Issues


In the "ilter sho$n+ timing 5et$een all signals must 5e s!nchroni1ed toachie>e results

Use SON0R*N*US logic+ as recommended "or FPGAs

Di""erent 0( signals control $hat %arts o" the %rocess are acti>ated 5! ena5ling FFs

I l t ti


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Im%lementation

Issues

Num5er re%resentation+ Bits and ord idths

Fi&ed %oint or "loating %oint3 Num5er re%resentation3

*%erations on the data $ill change the $ord si1e to maintain "ull

%recision Scaling

*>er"lo$+ under"lo$+ rounding

I l t ti


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Im%lementation

Issues

Num5er s!stems "or 5inar! re%resentations

Fi&ed %oint num5ers on FPGAsEFor no$J igh end FPGAs ha>e su%%ort "orsome "loating %oint o%erations

(ach s!stem has ad>antages and disad>antages "or im%lementations in digitalcircuits or arithmetic o%erations3

*ur e&am%les $ill use "i&ed %oint t$o?s com%lement re%resentations

Fi&ed %oint

Traditional Non traditional

BT$o?s com%lementB*ne?s com%lementBSign8MagnitudeBDiminshed8,

BSigned digitBRNS

Im%lementation


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Im%lementation

Issues

Fi&ed %oint 5inar! num5ers

Fi&ed %oint sets the decimal %oint at a "i&ed location $ithinthe 5inar! $ord

Im%lementation


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Im%lementation

Issues

*%eration results ha>e longer $ord lengths

Im%lementation


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Im%lementation

Issues

*>er"lo$+ saturation+ rounding - scaling

*>er"lo$ results $hen an arithmetic o%eration re=uires more5its than are a>aila5le in the result register

Rounding $ill hel% maintain the num5er o" 5its lo$

Ma! introduce o""sets or accumulati>e errors

Scaling can 5e used to reduce the num5er o" 5its used

I" all num5ers are 5et$een 8, and , multi%lication $ill result in a

num5er 5et$een 8, and ,

ill result in larger round8o"" or =uanti1ation errors

Im%lementation


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Im%lementation

Issues

*>er"lo$

0onsider these L85it t$o?s com%lement num5ers ,+ ,,

*>er"lo$J Maintaining the same num5er o" 5its gi>es an incorrect result3

An e&tra 5it "or the result $ill gi>e the correct ans$er

Sign e&tension ,, , ,, E6 5it num5er

To a>oid o>er"lo$ $e can use e&tra 5its in the accumulatorEguard 5its

Im%lementation


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Im%lementation

Issues

Saturation

In %re>ious o%eration+ , ,,

Sign e&tension ,, , ,, E6 5it num5er

Result is *Q 5ut has an e&tra 5it

*>er"lo$ is detected 5! chec7ing the old sign 5it %osition $ith

the ne$ sign 5it 5it 6 5it L# No *>er"lo$

Saturate the result

,, saturated to ,, Ema&imum num5er that can 5e

re%resented 5! L 5its

In "ilters+ ma!5e $e can saturate the result+ 5ut notthe intermediate >alues

Im%lementation


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Im%lementation

Issues

Rounding

Get rid o" least signi"icant 5its in resultEmulti%lication

Round coe""icients andor data%ath

Di""erent rounding methods Truncation+ round "loor+round ceiling+ round hal"8u%+ round hal"8e>en+ etc3

Re"er to Programma5le 9ogic Design 9ine article E:an 6+ .C

)An introduction to di""erent rounding algorithms/

Im%lementation


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Im%lementation

Issues

Rounding

Im%lementation


65/74

Im%lementation

Issues

Arithmetic *%erations and Im%lementation Structures

*%erations can 5e done using di""erent a%%roaches

Di""erent $ord $idths+ num5er re%resentations+ etc3

Di""erent cloc7 "re=uencies and data rates

*thers EDistri5uted arithmetic+ o%timi1ations

Se>eral "actors determine the t!%e o" im%lementation

Re=uired %recision

Re=uired data rates and sam%ling "re=uenc!

Resources a>aila5le in the FPGA

Dedicated DSP 5loc7s+ multi%liers+ logic+ memor!+ etc

*thers EPo$er3 (&ternal logic3

Im%lementation


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Im%lementation

Issues

Arithmetic *%erations Some multi%liersE"rom Andra7a?s $e5 site+ $$$3andra7a3com

Scaling Accumulator Ri%%le80arr! Arra! Ro$ Adder Tree

0om%uted Partial Product Partial Product 9UT

Im%lementation
http://www.andraka.com/http://www.andraka.com/


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Im%lementation

Issues

Structures+ 0alculations and *%timi1ations

Filter structures

Pi%elining

Po$er o" . o%erations

0ordic algorithms

Resource sharing

9oo7 u% ta5les "or o%erations+ loo7 u% ta5le o%timi1ation

T!%e o" memor! used E5loc7 or distri5uted

(tc3

Im%lementation


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Im%lementation

Issues

Filter Structures E"rom Peled and 9iu %a%er

Im%lementation


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Im%lementation

Issues

Pi%elining

Im%lementation


70/74

Im%lementation

Issues

*%erations and Structures

Re"er to %a%ers and articles

)Multi%lication in FPGAs/+ Ra! Andra7a+ $$$3andra7a3com

)FPGAs the high end alternati>e "or DSP a%%lications/+ 0hris Dic7+DSP (ngineering

)A Ne$ ard$are Reali1ation o" Digital Filters/+ Peled and B 9iu+I((( Trans on Acoust3+ S%eech+ Signal Processing+ Dec3 ,46

)A%%lication o" Distri5uted Arithmetic to Digital Signal Processing ATutorial Re>ie$)+ Stanle! hite+ I((( ASSP Maga1ine+ :ul! ,K

)igh S%eed Binar! Addition)+ Ro5ert :ac7son+ Sunil Tal$ar+ I(((Signals+ S!stems and 0om%uters+ .6

(tc3
http://www.andraka.com/http://www.andraka.com/


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o$ do $e go a5out doing DSP on an FPGA#

The Disintegration o" the

Persistence o" Memor!

Sal>ador Dali+ ,6

Im%lementation


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Im%lementation

Issues

T!%ical DSP design "lo$

Tas7 or7 onH

Design Simulate Models

0ode 0om%ile Simulate 0odeEAssem5l!+ 0+ D9s

Run 8 Test De5ug Plat"orm

This is >alid "or 0PU+ DSP or FPGA 5ased a%%roachesH $e are%ro5a5l! more care"ul i" 5uilding and ASI03

Im%lementation


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Im%lementation

Issues

Possi5le design "lo$s

0ode85ased

Model85ased

Mi&ed

Tools#


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A 5asic e&am%le Filtering

Three A%%aritions

o" the 2isage o" Gala

sase2011-dsp con fpga

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