pac proiect

Universitatea Politehnica Bucuresti

Facultatea de Transporturi

Profesor Indrumator Student

Petrescu Ionel Nae Adrian

Cuprins

1. Schema electrica

2. Descrierea circuitului

3. Cablaj imprimat (PCB)

4. Fisierul sursa PSpice (.cir)

5. Fisiere rezultate ( .out)

6. Grafice

R1

1kΩ

R2

68kΩ

A1

555_

VIR

TU

AL

GND

DIS

OUT

RST

VCC

THR

CON

TRI

A2

555_

VIR

TU

AL

GND

DIS

OUT

RST

VCC

THR

CON

TRI

C1

10µF

C2

100n

F

R3

10kΩ

R4

10kΩ

R5

10kΩ

C3

100n

F

C4

100µ

F

R6

8.0M

Ω

V1

5 V

2 3 0

6

1

5

9

7

811

0

10

1.Schema electrica a circuitului

2. Descrierea circuitului – Sirena de politie

Circuitul produce un sunet similar unei sirene de politie, utilizand doua circuite

555.

555 este un circuit integrat, folosit intr-o mare varietate de aplicatii cu timere,

generatoare de puls si oscilatoare. A fost creat in 1970 de Hans R Camenzind si

comercializat in 1971 de Signetics (acum NXP Semiconductors). Aceasta

componenta este folosita si astazi deoarece este usor de utilizat, are un pret

scazut si este stabil.Peste un milliard de unitati sunt fabricate anual.

Circuitul foloseste doua timere 555 pentru a produce un sunet ce oscileaza.

Variatia voltajului aplicat pinului 5 produce modificarea frecventei celui de al

doilea oscillator: creste sau scade.

Iesirea primului 555 este conectat la pinul 5 al celui de al doilea 555, controland

voltajul aplicat. Astfel, semnalul de iesire al celui de al doilea 555 este modulat de

frecventa primului 555, provocand efectul de sirena. Variatia voltajului aplicat

pinului 5 produce modificarea frecventei celui de al doilea oscillator.

Pe scurt, frecventa semnalului ce iese din cel de al doilea 555 este controlata de

iesirea primului 555.

555 are trei moduri de functionare:

- Modul Monostabil : functioneaza ca un generator

de puls

- Modul Astabil : functioneaza ca un oscillator

- Modul Bistabil sau Trigger Schmidt

In acest circuit 555 functioneaza in modul astabil, astfel ca, 555 genereaza un flux

continuu de impulsuri dreptunghiulare avand o anumita

frecventa.

Rezistorul R1, R2 si condensatorul C1 permit utilizarea in modul astabil, 555

comportandu-se ca un oscillator. In modul astabil, frecvența curentului de puls

depinde de valorile lui R1, R2 și C:

f=

( ) ( )

Aplicand o tensiune la pinul CTRL ( Voltage Control) se pot modifica

carecteristicile de sincronizare ale dispozitivului. In cele mai multe aplicatii pinul

CTRL nu este utilizat. De obicei, se conecteaza un condensator de 10nF intre

acesta si masa, pentru a preveni interferentele.

Condensatorul electrolitic conectat in serie cu difuzorul are rolul de a bloca

component continua, prevenind astfel defectarea bobinei difuzorului.

Circuitul poate fi alimentat la tensiuni cuprinse intre 5 – 15 V.

3. Cablaj imprimat (PCB)

4.Fisierul sursa ( .cir)

** Design1 **

xA2 0 2 10 4 7 2 3 4 555d

.LIB eval.lib

xA1 0 9 6 4 8 9 1 4 555d

vV1 4 0 dc 5 ac 0 0

rR8 11 0 8

cC4 10 11 0.0001

cC3 9 0 1e-005

rR5 4 3 10000

rR4 3 2 10000

rR1 4 1 1000

cC2 2 0 1e-007

cC1 8 0 1e-007

rR3 6 7 10000

rR2 1 9 68000

.TRAN 10ms 100ms

.TF V(1,2) Vv1

.DC VV1 0 5 0.5

.PROBE

.END

5.Fisiere rezultate ( .out)

**** 01/08/14 11:08:29 *********** Evaluation PSpice (Nov 1999) **************

** Design1 **

**** CIRCUIT DESCRIPTION

******************************************************************************

xA2 0 2 10 4 7 2 3 4 555d

.LIB eval.lib

xA1 0 9 6 4 8 9 1 4 555d

vV1 4 0 dc 5 ac 0 0

rR8 11 0 8

cC4 10 11 0.0001

cC3 9 0 1e-005

rR5 4 3 10000

rR4 3 2 10000

rR1 4 1 1000

cC2 2 0 1e-007

cC1 8 0 1e-007

rR3 6 7 10000

rR2 1 9 68000

.TRAN 10ms 100ms

.TF V(1,2) Vv1

.DC VV1 0 5 0.5

.PROBE

.END

**** Generated AtoD and DtoA Interfaces ****

*

* Analog/Digital interface for node 4

*

* Moving xA1.u1:CLRBAR from analog node 4 to new digital node 4$AtoD

X$4_AtoD1

+ 4

+ 4$AtoD

+ 4

+ 0

+ atod_555

+ PARAMS: CAPACITANCE= 0

* Moving xA2.u1:CLRBAR from analog node 4 to new digital node 4$AtoD2

X$4_AtoD2

+ 4

+ 4$AtoD2

+ 4

+ 0

+ atod_555

+ PARAMS: CAPACITANCE= 0

*


* Moving xA2.u1:Q1 from analog node 10 to new digital node 10$DtoA

X$10_DtoA1

+ 10$DtoA

+ 10

+ 4

+ 0

+ dtoa_555

+ PARAMS: DRVH= 96.4 DRVL= 104 CAPACITANCE= 0

*


*

* Moving xA1.u1:Q1 from analog node 6 to new digital node 6$DtoA

X$6_DtoA1

+ 6$DtoA

+ 6

+ 4

+ 0

+ dtoa_555


*

* Analog/Digital interface for node xA2.qb

*

* Moving xA2.u1:QBAR1 from analog node xA2.qb to new digital node xA2.qb$DtoA

X$xA2.qb_DtoA1

+ xA2.qb$DtoA

+ xA2.qb

+ 4

+ 0

+ dtoa_555


*

* Analog/Digital interface for node xA1.qb

*

* Moving xA1.u1:QBAR1 from analog node xA1.qb to new digital node xA1.qb$DtoA

X$xA1.qb_DtoA1

+ xA1.qb$DtoA

+ xA1.qb

+ 4

+ 0

+ dtoa_555


*

* Analog/Digital interface power supply subcircuits

X$DIGIFPWR 0 DIGIFPWR


** Design1 **

**** MOSFET MODEL PARAMETERS

******************************************************************************

xA2.nchan xA1.nchan

NMOS NMOS

LEVEL 1 1

L 100.000000E-06 100.000000E-06

W 100.000000E-06 100.000000E-06

VTO 0 0

KP 20.000000E-06 20.000000E-06

GAMMA 0 0

PHI .6 .6

LAMBDA 0 0

IS 10.000000E-15 10.000000E-15

JS 0 0

PB .8 .8

PBSW .8 .8

CJ 0 0

CJSW 0 0

CGSO 1.000000E-12 1.000000E-12

CGDO 1.000000E-12 1.000000E-12

CGBO 1.000000E-12 1.000000E-12

TOX 0 0

XJ 0 0

UCRIT 10.000000E+03 10.000000E+03

DIOMOD 1 1

VFB 0 0

LETA 0 0

WETA 0 0

U0 0 0

TEMP 0 0

VDD 0 0

XPART 0 0


** Design1 **

**** Digital Input MODEL PARAMETERS

******************************************************************************

din555

FILE DSO_DTOA

FORMAT 6

TIMESTEP 100.000000E-12

S0NAME 0

S0TSW 700.000000E-12

S0RLO 100

S0RHI 1.000000E+06

S1NAME 1

S1TSW 700.000000E-12

S1RLO 1.000000E+06

S1RHI 300

S2NAME x

S2TSW 700.000000E-12

S2RLO 200

S2RHI 200

S3NAME r

S3TSW 700.000000E-12

S3RLO 200

S3RHI 200

S4NAME f

S4TSW 700.000000E-12

S4RLO 200

S4RHI 200

S5NAME z

S5TSW 700.000000E-12

S5RLO 200.000000E+03

S5RHI 200.000000E+03


** Design1 **

**** Digital Output MODEL PARAMETERS

******************************************************************************

xA2.cmp xA1.cmp do555

FILE DSO_ATOD DSO_ATOD DSO_ATOD

FORMAT 6 6 6

CHGONLY 1 1 1

TIMESTEP 100.000000E-12 100.000000E-12 100.000000E-12

S0NAME 0 0 X

S0VHI 2

S0VLO -500 -500 .8

S1NAME 1 1 0

S1VHI 500 500 .8

S1VLO -1.5

S2NAME R

S2VHI 1.4

S2VLO .8

S3NAME R

S3VHI 2

S3VLO 1.3

S4NAME X

S4VHI 2

S4VLO .8

S5NAME 1

S5VHI 50

S5VLO 2

S6NAME F

S6VHI 2

S6VLO 1.3

S7NAME F

S7VHI 1.4

S7VLO .8


** Design1 **

**** Digital Gated FF MODEL PARAMETERS

******************************************************************************

xA2.t_srff xA1.t_srff

TPDQLHMN 0 0

TPDQLHTY 0 0

TPDQLHMX 0 0

TPDQHLMN 0 0

TPDQHLTY 0 0

TPDQHLMX 0 0

TPGQLHMN 0 0

TPGQLHTY 0 0

TPGQLHMX 0 0

TPGQHLMN 0 0

TPGQHLTY 0 0

TPGQHLMX 0 0

TPPCQLHMN 48.000000E-09 48.000000E-09

TPPCQLHTY 120.000000E-09 120.000000E-09

TPPCQLHMX 192.000000E-09 192.000000E-09

TPPCQHLMN 0 0

TPPCQHLTY 0 0

TPPCQHLMX 0 0

TWGHMN 0 0

TWGHTY 0 0

TWGHMX 0 0

TWPCLMN 0 0

TWPCLTY 0 0

TWPCLMX 0 0

TSUDGMN 0 0

TSUDGTY 0 0

TSUDGMX 0 0

TSUPCGHMN 0 0

TSUPCGHTY 0 0

TSUPCGHMX 0 0

THDGMN 0 0

THDGTY 0 0

THDGMX 0 0


** Design1 **

**** Digital Delay Line MODEL PARAMETERS

******************************************************************************

xA2.dlymod xA1.dlymod

DLYMN 166.666700E-09 166.666700E-09

DLYTY 166.666700E-09 166.666700E-09

DLYMX 166.666700E-09 166.666700E-09


** Design1 **

**** Digital IO MODEL PARAMETERS

******************************************************************************

xA2.io_555 xA1.io_555 io_std io_stm

DRVL 104 104 104 0

DRVH 96.4 96.4 96.4 0

AtoD1 atod_555 atod_555 AtoD_STD

AtoD2 atod_555 atod_555 AtoD_STD_NX

AtoD3 atod_555 atod_555 AtoD_STD

AtoD4 atod_555 atod_555 AtoD_STD_NX

DtoA1 dtoa_555 dtoa_555 DtoA_STD DtoA_STM




TSWHL1 1.373000E-09

TSWHL2 1.346000E-09

TSWHL3 1.511000E-09

TSWHL4 1.487000E-09

TSWLH1 3.382000E-09

TSWLH2 3.424000E-09

TSWLH3 3.517000E-09

TSWLH4 3.564000E-09

TPWRT 100.000000E+03 100.000000E+03 100.000000E+03 100.000000E+03


** Design1 **

**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C

*****************************************************************************

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

( 1) 5.0000 ( 2) 5.0000 ( 3) 5.0000 ( 4) 5.0000

( 6) 4.9722 ( 7) 4.0942 ( 8) 3.3333 ( 9) 5.0000

( 10) 4.9985 ( 11) 0.0000 (xA1.qb) 500.0E-06 (xA2.qb) 500.0E-06

($G_DGND) 0.0000 ($G_DPWR) 5.0000

(xA1.botm) 1.6667 (xA2.botm) 2.0471

DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE

( xA1.s) : 0 (xA2.strt) : 0 ( xA2.r) : 1 ( xA1.hi) : 1

( xA2.sd) : 0 ( xA2.s) : 0 ( 10$DtoA) : 1 ( xA2.rd) : 1

( 6$DtoA) : 1 ( xA1.sd) : 0 ( 4$AtoD2) : 1 ( xA1.r) : 1

(xA2.qb$DtoA) : 0 ( 4$AtoD) : 1 ( xA1.rd) : 1 (xA1.strt) : 0

( xA2.hi) : 1 (xA1.qb$DtoA) : 0

VOLTAGE SOURCE CURRENTS

NAME CURRENT

vV1 -3.056E-04

X$DIGIFPWR.VDPWR -5.000E-06

X$DIGIFPWR.VDGND -5.000E-06

TOTAL POWER DISSIPATION 1.55E-03 WATTS

**** SMALL-SIGNAL CHARACTERISTICS

V(1,2)/vV1 = 4.523E-06

INPUT RESISTANCE AT vV1 = 1.636E+04

OUTPUT RESISTANCE AT V(1,2) = 2.100E+04


** Design1 **

**** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C

******************************************************************************

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

( 1) 5.0000 ( 2) 5.0000 ( 3) 5.0000 ( 4) 5.0000

( 6) 4.9722 ( 7) 4.0942 ( 8) 3.3333 ( 9) 5.0000

( 10) 4.9985 ( 11) 0.0000 (xA1.qb) 500.0E-06 (xA2.qb) 500.0E-06

($G_DGND) 0.0000 ($G_DPWR) 5.0000

(xA1.botm) 1.6667 (xA2.botm) 2.0471

DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE

( xA1.s) : 0 (xA2.strt) : 0 ( xA2.r) : 1 ( xA1.hi) : 1

( xA2.sd) : 0 ( xA2.s) : 0 ( 10$DtoA) : 1 ( xA2.rd) : 1

( 6$DtoA) : 1 ( xA1.sd) : 0 ( 4$AtoD2) : 1 ( xA1.r) : 1

(xA2.qb$DtoA) : 0 ( 4$AtoD) : 1 ( xA1.rd) : 1 (xA1.strt) : 0

( xA2.hi) : 1 (xA1.qb$DtoA) : 0

VOLTAGE SOURCE CURRENTS

NAME CURRENT

vV1 -3.056E-04

X$DIGIFPWR.VDPWR -5.000E-06

X$DIGIFPWR.VDGND -5.000E-06

TOTAL POWER DISSIPATION 1.55E-03 WATTS

JOB CONCLUDED

TOTAL JOB TIME 1.20


**** CIRCUIT DESCRIPTION

******************************************************************************

6.Grafice

pac proiect

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