verilog coding

VERILOG CODINGMealy and Moore Machines

-PREM RANJAN

14ESP003

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MEALY MACHINE

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module state(x, clk, state, z); // Mealy FSM

input x, clk;

output z;

output [1:0] state;

reg z;

reg [1:0] state;

parameter S0=2’b00,

S1=2’b01;

initial

begin

state=S0;

z=0;

end 3

always @(negedge clk) // Next-State

case(state)

S0: if (x==0) state=S1;

else if (x==1) state=S0;

S1: if (x==0) state=S1;

else if (x==1) state=S0;

endcase

always@(state or x) // Output

case(state)

S0: if (x==0) z=0;

else if (x==1) z=0;

S1: if (x==0) z=0;

else if (x==1) z=1;

endcase

endmodule

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MOORE MACHINE

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module state(x, clk, state, z); // Moore FSM

input x, clk;

output z;

output [1:0] state;

reg z;

reg [1:0] state;

parameter S0=2’b00,

S1=2’b01,

S2=2’b10;

initial

begin

state=S0;

z=0;

end6

always@(negedge clk) // Next-State

case(state)

S0: if (x==0) state=S1;

else if (x==1) state=S0;

S1: if (x==0) state=S1;

else if (x==1) state=S2;

S2: if (x==0) state=S1;

else if (x==1) state=S0;

endcase

always@(state) // Output

case(state)

S0: z=0;

S1: z=0;

S2: z=1;

endcase

endmodule

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