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Introduction to Verilog HDL

By-

Abhinav VishnoiAssistant Professor

Lovely Professional University

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Verilog

Design Styles

Behavioral Design

Dataflow Design

Structural Design

Mixed Design

History

-The verilog HDL was developed by Gateway Design

Automation in 1983

-The language was placed in the public domain in 1990

-Open Verilog International (OVI) was formed to promote

verilog.

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Verilog Features

Primitive Logic Gates and, or, nand

It provides flexibility in programming because of

USER-DEFINED PRIMITIVES (UDP)

Switch Level modeling primitive gates PMOS,

NMOS, CMOS,RPMOS,RNMOS,RCMOS

Explicit language constructs are provided for

specifying pin-to-pin delays, path delays and timing

checks of a design

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Traditional vs. Hardware Description

Languages

Procedural programming languages provide the howor

recipes

for computation

for data manipulation

for execution on a specific hardware model

Hardware description languages describea system

Systems can be described from many different points of

view

Behavior: what does it do?

Structure: what is it composed of? Functional properties: how do I interface to it?

Physical properties: how fast is it?

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Usage

Descriptions can be at different levels of abstraction

Switch level: model switching behavior of transistors

Register transfer level: model combinational and

sequential logic components

Descriptions can used for

Simulation

Verification, performance evaluation

Synthesis

First step in hardware design

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Design process

Design and implement a simple unit permitting to

speed up encryption with RC5-similar cipher with

fixed key set on 8031 microcontroller. Unlike in

the experiment 5, this time your unit has to be able

to perform an encryption algorithm by itself,

executing 32 rounds..

LibraryIEEE;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entityRC5_core isport(

clock, reset, encr_decr: instd_logic;

data_input: instd_logic_vector(31downto0);

data_output: outstd_logic_vector(31downto0);

out_full: instd_logic;

key_input: instd_logic_vector(31downto0);

key_read: outstd_logic;

);

endAES_core;

Specification

Verilog HDL description (Your Verilog HDL Source

Files)

Functional simulation

Synthesis

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Design process (2)

Configuration

Timing simulation

On chip testing

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Alternatives

The Verilog hardware description language

Finding increasing use in the commercial world

SystemVerilog gaining prominence

VHDL dominates the aerospace and defense worlds

Programming language based design flows

SystemC

C++ with additional hardware-based language elements

C-based design flows

C + extensions as well as ANSI C based

Other

Java, MATLAB, and specialized languages

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Simulation Tools

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Implementation

After synthesis the entire implementation process is

performed by FPGA vendor tools

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Implementation