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DIVYA SHAH25/02/09

VERILOG HARDARE DESCRIPTIONLANGUAGE

LECTUER-2BASIC CONCEPTS

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LEXIAL CONVENTIONS

SAME AS C PROGRAMMING LANGUAGE

VERILOG IS A CASE SENSITIVE .

ALL KEYWORDS ARE IN LOWERCASE.

HAVE CERTAIN STREAM OF TOKENS.TOKENS CANBE COMMENTS,NUMBERS,STRINGS,IDENTIFIERS

AND KEYWORDS.

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1 . WHITE SPACE

BLANK SPACE (\b)

TABS (\t)

NEWLINES (\n)

THEY ARE GENERALLY IGNORED BY VERILOGEXCEPT WHEN IT SEPARATES TOKENS

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2.COMMENTS

ONE LINE COMMENTS START WITH (//)

MULTIPLE LINE COMMENTS START WITH (/*) AND

ENDS WITH (*/)

MULTIPLE LINE COMMENTS CAN¶T BE NESTED BUTSINGLE LINE COMMENTS CAN BE NESTED IN

MULTIPLE LINE COMMENT.Eg. /*this is /*an illegal*/comment*/

/*this is //a legal comment*/

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3 .OPERATORS

Arithmetic Operators+, -, *, /, %(modulas),**(power)

Bitwise Operators| :bitwise or &:bitwise and~:bitwise not^:bitwise xor ~^or^~:bitwise xnor

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4 -valued bitwise and logic

0 1 X Z

0 0 0 0 01 0 1 X X

X 0 X X XZ 0 X X X

Output 0 if one inputis 0

Output X if bothinputs are gibberish

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Logical Operators

! Not&& and| | or

Relational operators>,<,>=,<=

Equity operators==, !=,===(case equity),!==(case inequity)

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Reduction operators

it takes only one operand and yield a1

bitresult&,|,~&,~|,^,^~

Shift Operators>> right shift<< left shift

>>>arithmetic right shift<<< airthmetic left shift

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Concatenation operator { }

Ternary operator Essentially an if-then-else statement.

Uses two operators - ?, :Exampleresult = a ? b : c;

The first operand (a) is logicallyevaluated. If true second operand(b) isreturned otherwise third opearnd(c) isreturned.

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4 .Number representation

In verilog sized numbers are represented using thefollowing format

Number of bits µ radix value

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Radix

µb or µB binayµd or µD decimal (Default)µh or µH Hexa decimalµo or µO Octal

Examples4 ¶b0111

16 ¶habcd16 ¶d255

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Numbers that are specified without a base format thenthey are decimal no. by default

Numbers that are written without a size specification,have a default no. of 3 2bits.

Eg: 2 346 5//this is 3 2 bit decimal no.

µhc3 //this is 3 2 bit hex no.

Negative numbers can be specified using a minus signbefore the size of a constant number.

Underscore is allowed anywhere in a no. except the firstcharacter

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5.STRING:SEQUENCE OF CHARACTERS ENCLOSED BY DOUBLEQUOTES

6.IDENTIFIERS & KEYWORDS:KEYWORDS ARE SPECIAL IDENTIFIERS RESERVED TO

DEFINE THE LANGUAGE CONSTRUCTSKEYWORDS ARE IN LOWERCASEEg: regIDENTIFIERS ARE NAMES GIVEN TO OBJECTS THAT THEYCAN BE REFERENCED IN DESIGN

THEY ARE MADE UP OF ALPHANUMERIC CHARACTERS ANDTHE UNDERSCORE OR DOLLER SIGN BUT CANT START WITH

_ AND $THEY ARE ALSO CASE SENSITIVE

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DATA TYPESVALUE SETS:Verilog¶s nets and registers hold four-valued data0, 1

Obvious

ZOutput of an undriven tri-state driver Models case where nothing is setting a wire¶s value

XModels when the simulator can¶t decide the valueInitial state of registersWhen a wire is being driven to 0 and 1 simultaneouslyOutput of a gate with Z inputs

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Netsused to interconnect modules and primitives

The following net types supported in verilog

Net Type Descriptionwire Default net type

tri Another name for wire

wand Wired ANDtriand Another name for wandwor Wired ORtrior Another name for wor tri1 Wire with built-in pulluptri0 Wire with built-in pulldown

supply 1 Always 1

supply0 Always 0trireg Storage node for switch level modeling

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Default width of net object is 1 -bitNet objects can have width more than 1 -bit

Examplewire a,b,c; /* width = 1 bit */wire[7:0] a /* width = 8 bits */

wor[2:0] c; /* width = 3 bits */supply 1 vcc; /* width = 1 bit */supply0 gnd /* width = 1 bit */

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Registers

Registers are used for modeling in procedural block.Registers can be 1 -bit wide or declared as vectors.Registers are unsigned.Keyword used reg

Examplesreg a,b,c; /* 1-bit register */reg [15:0] a; /* 16-bit register */reg [0:3] r; /* 4-bit register */reg [15:12] a /* refers to 4 most significant bits of a */

a[15] // bit 15 of register aa[15-:3] // starting bit 15,width 3 or a[15:13]

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Memories

Memories are arrays of registers .

Memory declaration is similar to a reg declarationwith the addition of the range of words in thememory.

Examplereg [7:0] b[0:15]; /*b is a memory of 16 8-bit words

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Integers and realsIntegers are at least 3 2-bits wide.

Integers are signed.Integers are declared using the keywordinteger

A real data type holds a floating point number inIEEE format.Reals are at least 3 2-bit wide.Reals are declared using the keyword real

Examplesinteger number, count;real result, fraction;

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TimeUsed to represent current simulation time.Width of time data object is 64 -bits.Variables of type Time is declared usingkeyword time

Exampletime t 1 ,t2;

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ParametersParameters are run time constantsDefault size is 3 2-bits.You can declare parameters with rangesParameters may be stringsParameters are not used as a variableNote: Even though parameters are run time constants their values can be updated at compilation time.

Examplesparameter[ 13 :0] message = ³ Hello Verilog´;parameter size = 8;parameter msb = size- 1 ;

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SYSTE M TASKS

System task commands are used to perform systemrelated functions.

Examples

Printing messagesReading and Writing files.

All system task commands begin with $ symbol.

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Display system task commands

$dispalyCan be used to printout binary, decimal,

Hexadecimal or octal values.

Syntax$display(|optional format specifier |,

[value 1 ],[value2],«);

Examples$display (³%b %d´, num 1 , num2);$display (³First data´);$display (³Simulation time : %d´, sim_time);

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$ write

Same as $display except that $display put newline character at the end of the results where as$write does not.

Examples$write(³Verilog quick start´);$write(³%h %o´, hex_num, oct_num);

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$ strobeUsed when you want to print the values when allare changed at the current time unit.

Example$strobe(³The new values are %h, %d ³,

hex_val,dec_val);

$ monitor

Prints the data as they change.

Example$monitor (³reset time = %d´, reset);

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System task commands for file operations

$fopen

$fdisplay

$fwrite

$fmonitor

$fstrobe

$fclose